The present invention relates to a semiconductor memory device, and more particularly, to an address transfer circuit of a semiconductor memory device.
In a multi-functional system with a plurality of semiconductor devices, a semiconductor memory device serves as a data storage. The semiconductor memory device outputs data corresponding to an address inputted from a data processor, i.e., a central processing unit (CPU), to another device requesting the data, or stores data transferred from the data processor in unit cells corresponding to an address inputted together with the data.
The operations of the semiconductor memory device include an active operation, a write operation, and a read operation. In the active operation, the semiconductor memory device receives a row address and becomes an active state. Specifically, in the active operation, a word line corresponding to the row address is activated, and data signals of cells corresponding to the activated word line are amplified. In the write operation, data inputted together with a column address are stored in cells corresponding to the column address in response to a write command. In the read operation, data of cells corresponding to an external column address are outputted in response to a read command.
The semiconductor memory device includes a plurality of banks, each of which has a plurality of unit cell groups. A row decoder for decoding a row address and a column decoder for decoding a column address are provided at each bank. The row decoder decodes an inputted row address and selects and activates one of a plurality of word lines provided in the bank.
The unit cells of one bank are grouped into a plurality of cell blocks. A plurality of cell block control units and a plurality of latch units are provided in the bank. The cell block control units control the corresponding cell blocks, and the latch units latch the decoded address signals outputted from the row decoder and transfers the latched address signals to the cell blocks.
As the semiconductor device is highly integrated, the bit number of the row address increases and thus the row decoder becomes more complicated.